As semiconductor devices are scaled down, the minimum feature size attainable with the use of traditional patterning techniques (e.g., about 5 nanometers), such as photolithography and e-beam lithography, are being reached. Therefore, there is increased interest in the use of alternative approaches to define device features using self-assembling layers that are generally self-assembled monolayers (SAMs). There have been attempts to fabricate closely spaced electrodes on substrates using SAMs which serve as spacers between electrodes. Attempts have also been made to use the SAMs as a channel region of a field-effect transistor (FET). Such processes, however, remain problematic because there is a low yield of functional devices, that is, devices that do not have short circuits or parasitic currents.
Accordingly, a semiconductor device having closely spaced electrodes separated by a self-assembled layer that is more resistant to short circuiting than existing semiconductor devices using SAMs electrode spacers, is needed.